|FPGA Design and VHDL Services|
With introduction of multi-million gate feature rich FPGAs over the last couple of years, FPGAs have reached new levels of performance and functionality. This has given new levels of integration onto a single chip, with FPGAs now being commonly used as the primary gate array logic solution in many system designs. Compared to ASICs, FPGAs reduce risk, reduce design costs, offer a much quicker design time and are programmable. 100,000 gate FPGAs can now be purchased for as little as £10.
PKL Design offers an extensive portfolio of FPGA Design and VHDL Services to augment and complement your existing development capability. This ranges from a complete FPGA design service to assistant in independent VHDL code reviews.
FPGA Design Flow
A typical FPGA design flow is illustrated in Figure 1.
Figure 1: Typical FPGA Design Flow
PKL Design can assist in any or all aspects of the FPGA design flow. PKL Design has expertise with various FPGA device families from the leading FPGA device vendors, coupled with vast experience in the use of industry standard FPGA synthesis tools, including Leonardo Spectrum, Synplicity Synplify and Synopsys FPGA Compiler II. This means PKL Design has the knowledge to help you achieve the most efficient implementation of your design, whether your overriding constraint is performance, area, power or a mixture of all three.
Due to the increased complexity associated with large gate array designs, it is not uncommon for a team of designers to be working on a single design. The availability of multi million FPGA devices is helping achieve the goal of System on a Chip (SoC), which is theincorporation of an entire system onto one chip. An essential part of SoC design is the requirement to leverage existing intellectual property (IP) to improve designer productivity. Reusable IP is essential to constructing SoCs in a reasonable amount of time. PKL Design can assist by undertaling your IP development.
Our IP development service allows you to accelerate the frontend design of your gate array solution by focusing on the creation of IP modules. The resulting database provided by PKL will be structured and verified, allowing fast trouble free integration and verification with the designís other modules. Support for module integration and system verification is provided with testbench components to facilitate a fast successful design cycle.
Figure 2 illustrates a typical IP development flow.
Figure 2: Typical IP Development Flow